Computer processors may be designed to handle various instruction sets. One such instruction set is the x86 instruction set. Processors may have vastly different micro-architecture for implementing the same instruction set. Ideally, processors have an internal operation (“op”) for each instruction in the instruction set. The op may be designed to accomplish the instruction in as few processing cycles as possible. However, having dedicated micro-architecture so that each instruction has a corresponding op can be expensive, both in terms of design costs and to amount of space the added micro-architecture requires in the processor.
The x86 instruction set has recently been expanded to include advanced vector extension (“AVX”) which are directed to floating point intensive processing operations and particularly architected for SIMD processing. Accordingly, it is desirable to have a processor configured to implement the these and other similar instruction sets and a method for the processor to execute the new instructions. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.